Network processors are generally used for analyzing and processing packet data for routing and switching packets in a variety of applications, such as network surveillance, video transmission, protocol conversion, voice processing, and internet traffic routing. Early types of network processors were based on software-based approaches with general-purpose processors, either singly or in a multi-core implementation, but such software-based approaches are slow. Further, increasing the number of general-purpose processors had diminishing performance improvements, or might actually slow down overall network processor throughput. Newer designs add hardware accelerators in a system on chip (SoC) architecture to offload certain tasks from the general-purpose processors, such as encryption/decryption, packet data inspections, and the like. These newer network processor designs are traditionally implemented with either i) a non-pipelined SoC architecture or ii) a fixed pipeline SoC architecture.
In a typical non-pipelined SoC architecture, general-purpose processors are responsible for each action taken by acceleration functions. A non-pipelined SoC architecture provides great flexibility in that the general-purpose processors can make decisions on a dynamic, packet-by-packet basis, thus providing data packets only to the accelerators or other processors that are required to process each packet. However, significant software overhead is involved in those cases where multiple accelerator actions might occur in sequence.
In a typical fixed-pipeline SoC architecture, packet data flows through the general-purpose processors and/or accelerators in a fixed sequence regardless of whether a particular processor or accelerator is required to process a given packet. For example, in a fixed sequence, a single accelerator within the fixed pipeline cannot be employed without employing the entire fixed pipeline. This fixed sequence might add significant overhead to packet processing and has limited flexibility to handle new protocols, limiting the advantage provided by using the accelerators.
Network processors typically employ a classification stage where each received data packet is examined to identify information about the packet, such as a source address, destination address(es) and a packet type to determine processing requirements of the packet. Based on the classification results, received packets are typically placed output queues to be scheduled for processing and transmission by the network processor based on scheduling, traffic management, or traffic shaping requirements of the network processor or destination devices in communication with the network processor.
Modification to the packet data might typically be performed subsequent to queuing It might be desirable to modify the packet data prior to the packet being placed into an output queue. Typically, packet classification and modification might be required to run simultaneously, which could slow both operations. Additionally, typical packet modifiers might be required to read and write the entire packet data. Further, if the network processor maintains packet ordering on a global basis, head of line blocking could occur where subsequent packets could not be processed until all prior (even unrelated) packets had completed processing in their entirety.